FIG. 8 illustrates a circuit diagram of a prior art semiconductor amplifier. In FIG. 8, reference numeral 1 designates a field effect transistor (FET) such as an HEMT or MESFET. Numeral 2 designates an input matching circuit provided at the input side of the FET 1, and numeral 3 designates an output matching circuit provided at the output side of the FET 1. Numeral 4 designates a gate bias circuit provided at the input side of the FET 1, and numeral 5 designates a drain bias circuit provided at the output side of the FET 1.
In the circuit thus configured, the respective bias circuits 4 and 5 are electrically isolated by means of choke coils or .lambda./4 lines to prevent leakage of high frequency signals of magnitudes higher than several hundreds of megahertz to the bias circuits. Generally, amplifiers used for mobile communications have to maintain low distortion if an input power increases, and such amplifier is therefore designed such an that its input and output matching circuits 2 and 3 have characteristics of high power and high efficiency. To maintain low distortion, the FET 1 has to have a gate breakdown voltage (V.sub.gdo) within a desired range.
More specifically, gate breakdown voltage (hereinafter also referred to as breakdown voltage) is generally preferred to be high, because low breakdown voltage allows a high current to flow through the gate, degrading reliability. In view of distortion, however, an FET having a high gate breakdown voltage, e.g., higher than the quadrature of a source voltage, has an inferior distortion characteristic. As is already known from experiments, a breakdown voltage ranging from double to the quadrature of a source voltage is preferred.
There are two reasons why high breakdown voltage causes inferior distortion.
1. Degradation of Distortion Due to Shifting of the Load Line
As shown in FIG. 9, it is known that when a gate breakdown voltage (V.sub.gdo) is high, the negative amplitude of the waveform of the gate voltage V.sub.g of an FET is much greater than the positive one, which fact is described by Watanabe et al in IEICE Transacrions on Electornics, vol. E79-C, No.5, May, 1996, pp611-613, with detailed calculations.
V.sub.gg in the figure indicates a gate voltage when no signal is input, and is applied as a bias from an exterior source to obtain a constant voltage, as shown in FIG. 8. A dashed line 6 in FIG. 9 shows a waveform of a gate voltage V.sub.g when a small signal is input. This waveform is approximately symmetric, in the negative and positive directions, with respect to the gate voltage V.sub.gg when no signal is input. However, when the input power is increased, due to the nonlinearity of the FET, this waveform becomes asymmetric, in the negative and positive directions, with respect to the gate voltage V.sub.gg when no signal is input, as represented by a solid line 7 in the figure. In an FET having a high breakdown voltage, since the waveform in the negative direction of the gate voltage V.sub.gg when no signal is input is not clipped, the waveform has a negative amplitude greater than the positive one as shown in the figure. At this time, since a constant bias is applied such that average gate voltage/V.sub.g =V.sub.gg, the waveform of the gate voltage V.sub.g is wholly shifted in a positive direction to maintain the average value. Due to the shift, when an input power is high, a load curve at a drain side of the FET (which corresponds to a solid line 7 in FIG. 10) tends to be shifted upward, in comparison with the curve when the input power has a lower value (which corresponds to a dashed line 6 in the figure). That is, as shown in FIG. 10, gate voltage V.sub.g is shifted in the positive direction. Since the mutual conductance g.sub.m of an FET is generally not constant with respect to gate voltage V.sub.g, that is, negative and positive values of a gate voltage V.sub.g are not equal, when the load line shifts with a change in input power as shown in FIG. 10, operations are performed in regions of different mutual conductances g.sub.m, resulting in increased distortion.
On the other hand, since a low gate breakdown voltage of an FET causes waveform clipping for a negative value of a gate voltage, the negative amplitude of the gate waveform is not great as shown in FIG. 11, and the waveform becomes more symmetrical with respect to the gate voltage V.sub.gg when no signal is input. Therefore, a shift of the gate voltage V.sub.g for maintaining the division of an average gate value by gate voltage V.sub.g occurs less in comparison with the case shown in FIG. 9, the load line hardly shifts as shown in FIG. 12, and operations are performed in a region of same mutual conductance, minimizing increased distortion.
Nevertheless, a too low breakdown voltage causes excessive clipping of a gate voltage V.sub.g, affecting symmetry of the waveform, and degrading reliability due to a high gate current as well. This means that there is an optimal range for breakdown voltage.
2. Amendment of Distortion by Changing Input Conductance
This is disclosed in IEEE Transactions On Microwave Theory and Techniques., vol 44, No. 12, December, 1996 by Yamada et al., with detailed calculations. FIG. 13 is a diagram illustrating a nonlinear equivalent circuit of Heterojunction Bipolar Transistor (HBT). In this HBT, main nonlinear parameters are a capacitance C.sub.be between the base and the emitter, an input conductance g.sub.be and an output conductance g.sub.ce, and it is considered that the input conductance g.sub.be is has an effect on waveform clipping of an input-side waveform, and the output conductance g.sub.ce has an effect on waveform clipping of an output-side waveform. In the case of an FET, an input conductance g.sub.be, an output conductance g.sub.ce, and a capacitance C.sub.be between the base and the emitter can be regarded as a contribution to the effect of a waveform clipping caused by an input-side breakdown voltage and a resistance component. There is a further contribution from drain conductance obtained from drain-side waveform clipping, and nonlinearity of a capacitance C.sub.gs between gate and source of the FET, respectively. This means that a description of the HBT can be applied to the FET, too, and thus we will hereinafter describe a HBT used in the document quoted.
In the circuit shown in FIG. 13, a change of a phase passing from an input side to an output side .DELTA..PHI. is calculated by following formula (1): ##EQU1##
If gain matching is performed at the input side, the numerator of the second term of the equation, .omega.C.sub.be +B.sub.s, is zero and no contribution of .DELTA.g.sub.be is obtained. A low distortion semiconductor amplifier generally uses a method intending to improve distortion by making a value obtained by the matching at the input side different from the value as a result of gain matching. This corresponds to selecting B.sub.s in such a way that a phase change caused by .DELTA.g.sub.ce .omega. and .DELTA.C.sub.be is canceled by .DELTA.g.sub.be. More specifically, distortion is improved by reducing .DELTA..PHI. using a change of conductance caused by waveform clipping at the input side. In applying this theory to an FET, it is not possible to improve distortion when the FET's breakdown voltage is too high, whereas improvement of distortion is possible when the breakdown voltage is low enough to cause clipping. This corresponds to a fact determined by experiment that, at an input level at which gain is compressed by 1 to 3 dB (about double or the quadrature of an operation source voltage), a breakdown voltage having a magnitude high enough to cause clipping is preferred.
As is known from the above-described two reasons, it does not follow that the higher a gate breakdown voltage (V.sub.gdo) in an FET is, the better it is, rather a gate breakdown voltage within a desired range is required.
However, controlling breakdown voltage of an FET is generally difficult because the voltage depends on a recess geometry and a surface condition of the FET, causing low yield and increasing processing cost of semiconductor amplifiers.
There is another type of semiconductor power amplifier for receiving high frequencies and amplifying and outputting them, which is disclosed in Japanese Published Patent Application Number H8-139542. In this amplifier, to realize low distortion and high efficiency, a current circuit is provided at a gate input part of an amplification FET so as to supply a current of a magnitude corresponding to a power of an input signal to a bias circuit of the amplification FET. According to the techniques described in the patent document, since the current circuit employed comprises a Zener diode and its current-voltage characteristic is set such that a breakdown voltage is equal to a pinch-off voltage of the FET, it is possible to obtain gain in a wide range by moving bias points to new positions parallel to themselves such that they can maintain a sinusoidal waveform. This is, however, intended to obtain gain in a wide range without increasing distortion rather than to reduce distortion. Further, it is not normal for a GaAs type microwave circuit to comprise a Zener diode, and the above-described problems such as high processing cost are unavoidable for this circuit, too. That is, this circuit also cannot realize higher breakdown voltage and low distortion which are the goals for the present invention.
As described above, the conventional semiconductor amplifier circuit has the above configuration and must be designed so that a gate breakdown voltage (V.sub.gdo) of an FET can be set within a desired range. However, manufacturing the FET so that its breakdown voltage is within a desired range is technically difficult, causing inferior yield.